ASD Technical Report, Numéro 63,Partie 275

adaptive mode adder analog computer analog-digital converter arithmetic assumed binary Block Diagram capacitor cause failure channels circuit circuitry clock command converter core counter cycle delay line demonstration model digital computer digital layout diode logic Equation failure probability fan-in fan-out fault probability faults at voter filter fixed increment flight control computer flight control system flip-flops frequency function INCR initial conditions input operations Integrator Map iteration rate logic voter loop Mach Number machine mean lifetime mechanization microsecond N₁ non-redundant OHIO STATE UNIVERSITY P₂ performed PFiq pitch rate program board program memory pulse R-register redundant digital reset resistor result scale factor self-redundant shift register shown in Figure signal simulation solution rate strobe switch Table td te tf techniques th ti tj tj tk tl tk tl tm tl tm tn transistor two's complement voltage voter inputs voter outputs weighting function wires word zero crossing ΣΔ